Seminario Interdipartimentale di Algoritmica
 
 
 

Dipartimento di Informatica (ex-Scienze dell'Informazione) - D(S)I
via Salaria 113, piano terzo
Aula Seminari

Abstract:
A crucial task in the design of digital circuits is the efficient, possibly minimal, implementation of boolean functions. The standard synthesis with Sum of Products (SOP) minimization procedures, leads to two-level circuits. Minimizing more-than-two level circuits is a much harder task, but the size of the circuits can significantly decrease. In many cases three-level logic is a good trade-off among circuit speed, circuit size, and the time needed for the minimization procedure.

Function ``regularities'' have been studied in different contexts. We exploit the regularity of a given Boolean function, in order to decrease the time needed for its logical synthesis in any minimization framework. In particular, in this talk we present how to exploit function regularities for exact minimization of three- and two-level logic circuits.